1. Field of the Invention
The present invention relates to a method of fabricating a nonvolatile semiconductor memory device having a virtual ground array configuration.
2. Description of the Prior Art
In recent years, a nonvolatile semiconductor memory device having a virtual ground array configuration is a subject of interest as the technology of realizing high integration.
FIG. 10A through FIG. 10C are cross-sectional views illustrating steps in a method of fabricating a nonvolatile semiconductor memory device of a first background art (for example, see U.S. Pat. No. 6,803,284).
As illustrated with FIG. 10A, over a silicon substrate 601 having device isolation regions 600, a charge trapping layer 602, a first polysilicon film 603, and a silicon nitride film 604 are sequentially deposited. Then, the silicon nitride film 604 and the first polysilicon film 603 are selectively etched. Using the silicon nitride film 604 and the first polysilicon film 603 as a mask, bit line diffusion layers 608 are formed.
Next, as illustrated with FIG. 10B, a dielectric layer (not shown) is formed, and then polished by performing CMP. As a result, regions from which the silicon nitride film 604 and the first polysilicon film 603 are removed are filled with an insulation film 609.
Next, as illustrated with FIG. 10C, the silicon nitride film 604 is removed, and then a second polysilicon film 610 is formed.
FIG. 11A through FIG. 11C are cross-sectional views illustrating steps in a method of fabricating a nonvolatile semiconductor memory device of a second background art (for example, see U.S. Pat. No. 6,482,706).
It is not disclosed in the first background art but is generally known that pocket implantation is performed for the purposes of suppressing a short-channel effect and effectively producing hot carriers. The pocket implantation is performed in a region closer to a channel than the bit line diffusion layer is to the channel. The pocket implantation is opposite in conductivity type to bit line implantation. The method of forming a pocket implantation layer is disclosed in the second background art.
As illustrated with FIG. 11A, over a silicon substrate 701, a charge trapping layer 702 having a layered configuration and a first polysilicon film 703 are sequentially formed. Then, the first polysilicon film 703 is selectively etched. Using the first polysilicon film 703 as a mask, ion implantation 704 is performed to form pocket implantation layers 705.
Next, as illustrated with FIG. 11B, on a side surface of the first polysilicon film 703, a spacer 706 is formed. Then, using the first polysilicon film 703 and the spacer 706 as a mask, ion implantation 707 is performed to form bit line diffusion layers 708.
However, the nonvolatile semiconductor memory device according to the background arts has a problem that suppression of the short-channel effect in a miniaturized device is difficult.
In order to suppress the short-channel effect, it is necessary to form the pocket implantation layer closer to the channel than the bit line diffusion layer is to the channel. For that purpose, it is conceivable that the bit line diffusion layer is formed after the spacer is formed as disclosed in the second background art. However, in this case, the distance between bit lines has to be increased by the spacer to realize the same resistance for each bit line.
As another art for forming the pocket implantation layer closer to the channel than the bit line diffusion layer is to the channel, it is generally known to perform pocket implantation at an angle. In this case, an identical mask is used to perform pocket implantation at an angle of 25 degrees and to perform bit line implantation perpendicularly, which realizes a desired profile.
However, when pocket implantation is performed at an angle, the implantation is not performed in a later-described “shadow” region between adjacent gate electrodes. Therefore, an implantation angle may not be greatly increased, with the “shadow” region being ignored. In the first background art, the “shadow” region expands as the total height of the first polysilicon film 603 and the silicon nitride film 604 increases, and the size of a region acceptable as the “shadow” region reduces as the distance between adjacent first polysilicon films 603 narrows due to miniaturization.
FIG. 12 is a partially enlarged view which illustrates a cross sectional configuration of the first background art and with reference to which influence of the “shadow” region in the case of pocket implantation performed at an angle is described.
It is assumed that the distance between the adjacent first polysilicon films 603 is s, the length of the “shadow” region is x, the total height of the charge trapping layer 602, the first polysilicon film 603, and the silicon nitride film 604 is h, an implantation angle along a normal direction to a principal plane of the semiconductor substrate 601 is 0°, and an implantation angle inclined from the normal direction is θ. In this case, relational expressions as follows are to hold true.s>xx=h·tan(90−θ)=h/tan(θ)
According to the relational expressions, the problem of reducing the “shadow” region may be solved by lowering the total height h of the charge trapping layer 602, the first polysilicon films 603, and the silicon nitride film 604. However, since the silicon nitride film 604 is used later as a stopper film in the step of polishing by CMP, the silicon nitride film 604 is required to have a film thickness of about 100 nm to about 200 mm. Therefore, even if miniaturization is performed, the film thickness of the silicon nitride film 604 may not be reduced. In other words, even if miniaturization is performed, the length x of the “shadow” does not change, and thus the distance s between the adjacent first polysilicon films 603 can not be reduced.
As described above, the nonvolatile semiconductor memory device of the background arts has a problem that suppression of the short-channel effect in a miniaturized device is difficult.